ICS9169C-40 Datasheet, PDF (5/6 Pages) Integrated Circuit Systems – System Clock Chip

ICS169C-40
Technical Pin Function Descriptions
VDD/AVDD
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
• PCI (1:6)
• REF
This pin may be operated at any voltage between 3.0 and 5.5
volts. Clocks from the listed buffers that it supplies will
have a voltage swing from ground to this level. For the
actual guaranteed high and lowvoltage levels of these clocks,
please consult the AC parameter table in this data sheet.
GND/AGND
This is the power supply ground return pin for the chip.
XIN
This pin serves one of two functions. When the device is
used with a crystal, XIN acts as the input pin for the reference
signal that comes from the discrete crystal. When the device
is driven by an external clock signal, XIN is the device’
input pin for that reference clock. This pin also implements
an internal crystal loading capacitor that is connected to
ground. See the data tables for the value of the capacitor.
XOUT
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode ofoperation, XOUT
is an output signal that drives (or excites) the discrete crystal.
This pin also implements aninternal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
CPU (1:8)
These pins are the clock outputs that drive processor and
other CPU related circuitry that require clocks which are in
tight skew tolerance with the CPU clock. The voltage swing
of these clocks is controlled by that which is applied to the
VDDL (1:2) pin of the device. See the Functionality table at
the beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
PCI (1:6)
Outputs for PCI bus with a skew ≤ 250pS.A high current rate
of 60mA is available at 3.3V. These outputs are supplied from
VDD.
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
PCI pins. See the Funtionality table at the beginning of this
data sheet for a list of the specific frequencies, and the
selection codes that are necessary to produce these
frequencies. The device reads these pins at power-up. If a
"1" value is desired for a specific frequency selection bit,a
10K ohm restor must be connected from the apporapriate FS
pin to the VDD supply. If a "0" value is desired, then the 10K
resistor must be connected to ground.
REF
This is a fixed frequency clock that runs at the same frequency
as the input reference clock (typically 14.31818 MHz) is and
typically used to drive Video and ISA BUS requirements.
VDDL (1:2)
This is the power supply to the CPU clock drivers. This pin
may be operated "at any voltage" between 2.5 and 3.3 volts.
Clocks from the buffers that it supplies will have a voltage
swing form ground to this level. For the actual guaranteed
high and low voltage levels of these clocks. Please consult
the AC parameter table in this data sheet.
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