ICS9169C-27 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – Frequency Generator for Pentium Based Systems

ICS9169C-27
Technical Pin Function Descriptions
VDD
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. Fixed clock output buffers
This pin may be operated at any voltage between 3.0 and 5.5
volts. Clocks from the listed buffers that it supplies will
have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
GND
This is the power supply ground return pin for the internal
logic of the device as well as the following clock output
buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. CPU clock output buffers
D. Fixed clock output buffers
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the reference
signal that comes from the discrete crystal. When the device
is driven by an external clock signal, X1 is the device’ input
pin for that reference clock. This pin also implements an
internal crystal loading capacitor that is connected to ground.
See the data tables for the value of the capacitor.
X2
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is
an output signal that drives (or excites) the discrete crystal.
This pin also implements an internal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
CPU
This pin is the clock output that drives processor and other
CPU related circuitry that require clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of
these clocks is controlled by that which is applied to the
VDDC pins of the device. See note on VDDC (1:2). See the
Functionality table at the beginning of this data sheet for a
list of the specific frequencies that this clock operates at and
the selection codes that are necessary to produce these
frequencies.
BUS
This pin is the clock output that is intended to drive the
systems plug-in card bus. The voltage swing of these
clocks is control-led by the supply that is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
CPUL, BUS & SDRAM pins. See the Funtionality table at
the beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies. The
device reads these pins at power-up and stores the
programmed selection code in an internal data latch. (See
programming section of this data sheet for configuration
circuitry recommendations.
BSEL
This pin controls whether the BUS clocks will be synchronous
(run at half the frequency) with the CPU and CPUL clocks or
whether they will be asynchronous (run at a pre-programmed
fixed frequency) clock rate. It is a shared pin and is pro
grammed the same way as the frequency select pins.
VDDC (1:2)
These are the power supply pins for the CPU (1:6) and CPU
(7:12) clock buffers. By separating the clock power pins,
each group can receive the appropriate power decoupling
and bypassing necessary to minimize EMI and crosstalk
between the individual signals. VDDC1 can be reduced to
2.5V VDD for advanced processor clocks, which will bring
CPU (1:6) outputs at 0 to 2.5V output swings.
48 MHz
This is a fixed frequency clock that is typically used to drive
Super I/O peripheral device needs.
24 MHz
This is a fixed frequency clock that is typically used to drive
Keyboard controller clock needs.
REF
This is a fixed frequency clock that runs at the same frequency
as the input reference clock (typically 14.31818 MHz) is
and typically used to drive Video and ISA BUS
requirements.
VDDB
This power pin supplies the BUS clock buffers.
VDDF
This power pin supplies the 48/24 MHz clocks.
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