ICS9148-36 Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9148 - 36
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Must be 0 for normal operation
Bit 7 _{0 - ±0.25% Spread Spectrum Modulation}
1 - ±0.6% Spread Spectrum Modulation
Bit6 Bit5 Bit4 CPU Clock PCI
111
100
33.3
110
95.25
31.75
Bit
6:4
101
100
011
83.3
33.3
75
30
75
37.5
010
68.5
34.25
001
66.8
33.4
000
60
30
AGP
66.6
63.5
66.6
60
75
68.5
66.8
60
0 - Frequency is selected by hardware select,
Bit 3 Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
Must be 0 for normal operation
Bit 2 _{0 - Spread Spectrum center spread type.}
1 - Spread Spectrum down spread type.
Bit 1
0 - Normal
1 - Spread Spectrum Enabled
Bit 0
0 - Running
1- Tristate all outputs
PWD
0
Note1
0
0
0
0
Note 1. Default at Power-up will be for latched logic inputs
to define frequency. Bits 4, 5, 6 are default to 000,
and if bit 3 is written to a 1 to use Bits 6:4, then
these should be defined to desired frequency at same
write cycle.
Note: PWD = Power-Up Default
I²C is a trademark of Philips Corporation
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
40
-
41
43
44
PWD
1
X
X
1
1
1
1
1
Description
(Reserved)
FS2#
FS1#
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
X
1
X
1
1
1
1
1
Description
CPU3.3#_2.5
PCICLK_F (Act/Inact)
FS0#
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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