ICS8702 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDDI Input Power Supply Voltage
3.135
3.3
3.465
V
VDDO Output Power Supply Voltage
2.375
2.5
2.625
V
VIH
Input High Voltage All except CLK, nCLK
VDDI = 3.465V
2
3.8
V
VIL
VPP
VCMR
IIH
Input Low Voltage
Peak-to-Peak
Input Voltage
Common Mode
Input Voltage;
NOTE 1
Input High Current
All except CLK, nCLK
CLK, nCLK
CLK, nCLK
All except CLK
CLK
VDDI = 3.135V
LVPECL Levels
DCM, HSTL, LVDS, SSTL Levels
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
-0.3
0.15
1.8
0.31
0.8
V
1.3
2.4
1.3
5
µA
150
µA
All except CLK
VDDI = 3.465V, VIN = 0V
-150
µA
IIL
Input Low Current
CLK
VDDI = 3.465V, VIN = 0V
-5
µA
IDD
Quiescent Power Supply Current
VDDI = VIH = 3.465V
VIL = 0V
70
mA
VOH
Output High Voltage
VDDI = 3.135V, VDDO = 2.375V
IOH = -27mA
1.9
V
VOL
Output Low Voltage
VDDI = 3.135V, VDDO = 2.375V
IOL = 27mA
0.5
V
NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. The LVPECL values noted in Table 4B are for VCCI =
3.3V. VCMR for LVPECL will vary 1:1 with VCCI. Common mode input voltage for DCM, HSTL, LVDS and SSTL is defined as the crossover
voltage. See Figure 1.
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Maximum Input Frequency
250
MHz
tpLH
Propagation Delay, Low-to-High
0MHZ < f ≤ 200MHz
2.3
3.6
ns
tpHL
Propagation Delay, High-to-Low
0MHZ < f ≤ 200MHz
2.3
3.6
ns
tsk(b)
Bank Skew; NOTE 2
Measured on rising edge at VDDO/2
150
ps
tsk(o)
Output Skew; NOTE 3
Measured on rising edge at VDDO/2
200
ps
tsk(ω)
Multiple Frequency Skew; NOTE 4
Measured on rising edge at VDDO/2
250
ps
tsk(pp)
Part to Part Skew; NOTE 5
Measured on rising edge at VDDO/2
700
ps
tR
Output Rise Time; NOTE 6
30% to 70%
280
850
ps
tF
Output Fall Time; NOTE 6
tPW
Output Pulse Width
30% to 70%
0MHZ < f < 200MHz
f = 200MHz
280
850
ps
tCYCLE/2
- 0.5
tCYCLE/2
tCYCLE/2
+ 0.5
ns
2
2.5
3
ns
tEN
Output Enable Time; NOTE 6
f = 10MHz
6
ns
tDIS
Output Disable Time; NOTE 6
f = 10MHz
6
ns
NOTE 1: All parameters measured at fIN = 200MHz and VPP = 300mV unless noted otherwise. All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions.
NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8702
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REV. A - AUGUST 7, 2000