ICS8422004-01I Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8422004I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%,V_DDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
140
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] = 10
56
tsk(o) Output Skew; NOTE 1, 3
TBD
156.25MHz, (1.875MHz - 20MHz)
0.44
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
125MHz, (1.875MHz - 20MHz)
0.48
62.5MHz,(1.875MHz - 20MHz)
0.49
t_R / t_F
Output Rise/Fall Time
20% to 80%
410
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
170
136
68
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
TABLE 5B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
2.5V±5%,V
DDO
= 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
140
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] = 10
56
tsk(o) Output Skew; NOTE 1, 3
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz,(1.875MHz - 20MHz)
0.41
0.49
0.50
t_R / t_F
Output Rise/Fall Time
20% to 80%
380
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2 Please refer to the Phase Noise Plot.
NOTE 3 This parameter is defined in accordance with JEDEC Standard 65.
Maximum
170
136
68
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
8422004AGI-01
www.icst.com/products/hiperclocks.html
5
REV. B NOVEMBER 14, 2005