ICS8421004I-01 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8421004I-01
FEMTOCLOCKS™ CRYSTAL-TO-
HSTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, _DD = V_DDA = 3.3V±5%,V_DDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SEL[1:0] = 00
140
170
MHz
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] = 10
56
136
MHz
68
MHz
tsk(o) Output Skew; NOTE 1, 3
TBD
ps
156.25MHz, (1.875MHz - 20MHz)
0.44
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
125MHz, (1.875MHz - 20MHz)
0.48
ps
62.5MHz,(1.875MHz - 20MHz)
0.49
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
450
ps
50
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
2.5V±5%,
V
DDO
= 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SEL[1:0] = 00
140
170
MHz
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] = 10
56
136
MHz
68
MHz
tsk(o) Output Skew; NOTE 1, 3
TBD
ps
156.25MHz, (1.875MHz - 20MHz)
0.41
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
125MHz, (1.875MHz - 20MHz)
0.49
ps
62.5MHz,(1.875MHz - 20MHz)
0.50
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
420
ps
50
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2 Please refer to the Phase Noise Plot.
NOTE 3 This parameter is defined in accordance with JEDEC Standard 65.
8421004AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A MACH 29, 2005