ICS840004I-01 Datasheet, PDF (5/10 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, V_DDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_OUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 2
156.25
125
62.5
TBD
MHz
MHz
MHz
ps
156.25MHz, (1.875MHz - 20MHz)
0.48
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
125MHz, (1.875MHz - 20MHz)
0.59
ps
62.5MHz, (1.875MHz - 20MHz)
0.53
ps
t_L
PLL Lock Time
TBD
ms
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
450
ps
50
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
TABLE
5C.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
V
DDO
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical
156.25
f_OUT
Output Frequency
125
62.5
tsk(o) Output Skew; NOTE 1, 2
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
0.50
0.60
0.51
t_L
PLL Lock Time
TBD
t_R / t_F
Output Rise/Fall Time
20% to 80%
450
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ms
ps
%
840004AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 28, 2005