ICS83052I-01 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – 2-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83052I-01
2-BIT, 2:1,
SINGLE-ENDED MULTIPLEXER
TABLE 5B. AC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f
MAX
tp_LH
tp_HL
tsk(i)
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 5
250
MHz
2.7
ns
2.7
ns
38
ps
tsk(pp)
tjit
t_R / t_F
odc
Part-to-Part Skew; NOTE 2, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Integration Range:
12KHz - 20MHz
20% to 80%
TBD
ps
0.04
ps
550
ps
50
%
t_EN
Output Enable Time; NOTE 3
5
ns
t_DIS
Output Disable Time; NOTE 3
5
ns
MUX_ISOL MUX Isolation
@100MHz
45
dB
NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 1.8V ± 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
tp_LH
tp_HL
tsk(i)
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 5
250
MHz
3
ns
3
ns
38
ps
tsk(pp)
tjit
t_R / t_F
odc
Part-to-Part Skew; NOTE 2, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Integration Range:
12KHz - 20MHz
20% to 80%
TBD
ps
0.05
ps
595
ps
50
%
t_EN
Output Enable Time; NOTE 3
5
ns
t_DIS
Output Disable Time; NOTE 3
5
ns
MUX_ISOL MUX Isolation
@100MHz
45
dB
NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83052AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 24, 2004