ICS9250-27 Datasheet, PDF (4/14 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-27
Truth Table
FS2 FS1 FS0
X0 0
X0 1
0 10
0 11
1 10
111
CPU
Tristate
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Tristate
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
PCI
Tristate Tristate
TCLK/3 TCLK/6
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
IOAPIC
Tristate
Tristate
TCLK
TCLK/6
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
SpreadSpectrum
(1=On/0=Off)
26 48MHz 1
25 48MHz 0
49 CPUCLK2
PWD Description
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 36 SDRAM7
Bit 6 37 SDRAM6
Bit 5 39 SDRAM5
Bit 4 40 SDRAM4
Bit 3 42 SDRAM3
Bit 2 43 SDRAM2
Bit 1 45 SDRAM1
Bit 0 46 SDRAM0
PWD Description
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
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