ICS9148B-04 Datasheet, PDF (4/14 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9148 B -04
A. For the clock generator to be addressed by an I²C controller, the following address must be sent as a start sequence, with
an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D2(H)
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
B. The clock generator is a slave/receiver I²C component. It can "read back "(in Philips I²C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
ACK
Byte 0
ACK
Byte 1
ACK _{Byte 0, 1, 2, etc in sequence until STOP.}
D3(H)
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F.
To simplify the clock generator I²C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 6:4
Bit 3
Bit 2
Bit 1
Bit 0
Description
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit6 Bit5 Bit4 CPU clock
PCI
111
66.8
33.4(1/2 CPU)
110
60.0
30.0 (1/2 CPU)
101
75.0
37.5 (1/2 CPU)
100
83.3
33.3
011
68.5
34.5 (1/2 CPU)
010
83.3
41.65 (1/2 CPU)
001
75.0
32.0
000
50.0
25.0 (1/2 CPU)
0 - Frequency is selected by hardware select,
Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
PWD
0
Note 1
0
0
0
0
Note 1. Default at Power-up will be for latched logic
inputs to define frequency. Bits 4, 5, 6 are default
to 000, and if bit 3 is written to a 1 to use Bits
6:4, then these should be defined to desired
frequency at same write cycle.
Note: PWD = Power-Up Default
I²C is a trademark of Philips Corporation
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