ICS9148-26 Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9148 - 26
General I²C serial interface information
A. For the clock generator to be addressed by an I²C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D2(H)
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
B. The clock generator is a slave/receiver I²C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
ACK
Byte Count
Readback
Then Byte 0, 1, 2, etc. in
ACK _{sequence until STOP.}
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F.
To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
G.. At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled
output state).
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 6:4
Bit 3
Bit 2
Bit 1
Bit 0
Description
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit6 Bit5 Bit4
CPU clock
PCI
111
100.2
33.3 (CPU/3)
110
133.3²
33.3²
101
112.0²
37.3²
100
103
34.3 (CPU/3)
011
66.8
33.4 (CPU/2)
010
83.3
41.65(CPU/2)
001
75
37.5 (CPU/2)
000
50
25 (CPU/2)
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
PWD
0
Note1
0
0
0
0
Note1. Default at Power-up will be for
latched logic inputs to define
frequency. Bits 4, 5, 6 are default
to 000, and if bit 3 is written to a 1
to use Bits 6:4, then these should
be defined to desired frequency at
same write cycle.
Note2. Performance not guaranteed
Note: PWD = Power-Up Default
I²C is a trademark of Philips Corporation
4