ICS9147-14 Datasheet, PDF (4/7 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9147 - 14
Electrical Characteristics at 3.3V
V_DD = 3.0 – 3.7 V, T_A = 0 – 70° C unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Rise Time¹
Tr1
20pF load, 0.8 to 2.0V
CPU, IOAPIC, Fixed & REF
-
Fall Time¹
Tf1
20pF load, 2.0 to 0.8V
CPU, IOAPIC, Fixed & REF
-
Rise Time¹
Tr2
20pF load, 20% to 80%
CPU, IOAPIC, Fixed & REF
-
Fall Time¹
Rise Time¹
Fall Time¹
Rise Time¹
Tf2
20pF load, 80% to 20%
CPU, IOAPIC, Fixed& REF
-
Tr3
20pF load, 0.8 to 2.0V PCI, SDRAM
-
Tf3
20pF load, 2.0 to 0.8V PCI, SDRAM
-
Tr4
20pF load, 0.4 to 2.0V , CPU and
IOAPIC with VDDL = 2.5V
-
Fall Time¹
Tf4
20pF load, 2.0 to 0.4V, CPU and
IOAPIC with VDDL = 2.5V
-
Duty Cycle¹
Dt
20pF load @ VOUT=1.4V
All clocks except REF
45
Duty Cycle¹
DT2
20pF load @ VOUT=1.4V
REF outputs
40
Jitter, One Sigma¹
Tjis1
CPU & PCICLK Clocks; Load=20pF,
SDRAM; Load = 30pF
-
Jitter, Absolute¹
Tjab1
CPU & PCICLK Clocks; Load=20pF,
SDRAM; Load = 30pF
-250
Jitter, Cycle to Cycle
Jitter, One Sigma¹
Jitter, Absolute¹
Input Frequency¹
Logic Input Capacitance¹
Crystal Oscillator Capacitance¹
Power-on Time¹
Tjc-c
CPU
-
Tjis2
Fixed CLK; Load=20pF
-
Tjab2
Fixed CLK; Load=20pF
-5
Fi
12.0
CIN
Logic input pins
-
CINX
X1, X2 pins
-
ton
From VDD=1.6V to 1st crossing of
66.6 MHz VDD supply ramp < 40ms
-
Clock Skew¹
Tsk1
CPU to CPU or PCI to PCI;
Load=20pF; @1.4V (Same VDD)
-
Clock Skew¹
Tsk2
SDRAM to SDRAM;
Load=20pF; @1.4V
-
Clock Skew¹
Tsk3
CPU to PCICLK; Load=20pF; @1.4V
(CPU is early)
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
TYP
0.9
0.8
1.5
1.4
0.9
0.8
-
-
50
50
50
-
200
1
2
14.318
5
18
2.5
150
300
2.1
MAX
1.5
1.4
2.5
2.4
1.5
1.4
3.0
2.0
55
60
150
250
350
3
5
16.0
-
-
4.5
250
500
4
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
%
%
ps
ps
ps
%
%
MHz
pF
pF
ms
ps
ps
ns
4