ICS889834 Datasheet, PDF (4/7 Pages) Integrated Circuit Systems – LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER

Integrated
Circuit
Systems, Inc.
HiPerClockS™ Application Note
3.3V LVPECL DRIVER TERMINATION
AC Coupled Termination
For AC termination, the offset level needs to be taken care of after the AC capacitors. A bias circuit might be
required. The board design engineer needs to verify what type of receiver is being driven. A few examples of AC
couple termination are shown in this section.
In Figure 6, the R3 and R4 at the driver pins provide a current path for the LVPECL driver. R1 and R2 serve as
matched load termination. The power supply V_BB controls the offset level so that the signal offset fall within the
VCMR input requirement of the receiver. Figure 7 and Figure 8 are equivalent to Figure 5. The Figure 7 is
equivalent to V_BB=V_CC-2V. This offset is suitable for interfacing with HiPerClockS^TM CLK/nCLK input. Figure 8 is
equivalent to V =V -1.3V. This offset is suitable for interfacing with HiPerClockS^TM PCLK/nPCLK input. Figure 9
BB CC
shows AC termination with the offset bias voltage V_BB provided at the receiving end. Figure 10 shows AC
termination with the offset bias voltage V provided by the receiver device. In some cases, for the receiver with
BB
built-in bias resistors R1 and R2, the termination is shown in Figure 11.
VCCO=3.3V
U1
3v3 PECL Driver
Zo = 50 Td
C1
+
TL1
-
Zo = 50 Td
C2
R3
100-180
nTL1
R4
100-180
R2
R1
50
50
VBB
Figure 6 AC Coupled with V_BB power supply provided at the receiving end
www.icst.com/products/hiperclocks.html
4
Aug 02, 2002