ICS843004I-01 Datasheet, PDF (4/14 Pages) Integrated Circuit Systems – FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS843004I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 3D. LVPECL DC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V_OH
Output High Voltage; NOTE 1
V_OL
Output Low Voltage; NOTE 1
V_SWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to V_CCO - 2V.
V_CCO - 1.4
V_CCO - 2.0
0.6
V_CCO - 0.9
V_CCO - 1.7
1.0
Units
V
V
V
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
Units
MHz
Ω
pF
TABLE 5A. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SEL[1:0] = 00
140
170
MHz
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] =10
56
136
MHz
68
MHz
tsk(o) Output Skew; NOTE 1, 3
50
ps
156.25MHz (1.875MHz - 20MHz)
0.54
ps
tjit(Ø) RMS Phase Jitter; NOTE 2
125MHz (1.875MHz - 20MHz)
0.58
ps
62.5MHz (637KHz - 10MHz)
0.70
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
48
600
ps
52
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_CCO/2.
NOTE 2: Please refer to Phase Noise Plots on following page.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
140
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
F_SEL[1:0] =10
56
tsk(o) Output Skew; NOTE 1, 3
156.25MHz (1.875MHz - 20MHz)
0.54
tjit(Ø) RMS Phase Jitter; NOTE 2
125MHz (1.875MHz - 20MHz)
0.58
62.5MHz (637KHz - 10MHz)
0.74
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_CCO/2.
NOTE 2: Please refer to Phase Noise Plots on following page.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
170
136
68
50
600
52
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
843004AGI-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 11, 2005
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