ICS8430-71B Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430B-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD M
Inputs
Conditions
N S_LOAD S_CLOCK S_DATA
H
X
XX
X
X
X Reset. Forces outputs LOW.
L
L
Data Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data Data
L
L
H
XX
L
L
H
XX
↑
L
H
XX
↓
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
Data M divider and N output divider values are latched.
L
H
XX
L
L
H
XX
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
X
X Parallel or serial input do not affect shift registers.
↑
Data S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency
(MHz)
M Divide
256
M8
128
M7
64
M6
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
250
125
0
0
1
1
1
1
1
0
1
252
126
0
0
1
1
1
1
1
1
0
254
127
0
0
1
1
1
1
1
1
1
256
128
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
348
1
0
1
0
1
1
1
0
0
698
349
1
0
1
0
1
1
1
0
1
700
350
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of
16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
N2
N1
N0
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
1
1
0
1
2
1
1
0
4
1
1
1
8
8430BY-71
www.icst.com/products/hiperclocks.html
4
FOUT0, nFOUT0 Output Frequency
(MHz)
Minimum
Maximum
125
350
62.5
175
31.25
87.5
15.625
43.75
250
700
125
350
62.5
175
31.25
87.5
REV. A SEPTEMBER 20, 2005