ICS8430-61 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8430-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD M
H
X
X
Inputs
N S_LOAD
X
X
S_CLOCK
X
S_DATA
X
Conditions
Reset. Forces outputs LOW.
L
L
Data Data
X
L
↑
Data Data
L
L
H
XX
L
L
H
XX
↑
L
H
XX
↓
L
H
XX
L
L
H
XX
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
Data M divider and N output divider values are latched.
X
X Parallel or serial input do not affect shift registers.
↑
Data S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency
(MHz)
M Divide
256
M8
128
M7
64
M6
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
250
250
0
1
1
1
1
1
0
1
0
251
251
0
1
1
1
1
1
0
1
1
252
252
0
1
1
1
1
1
1
0
0
253
253
0
1
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
498
498
1
1
1
1
1
0
0
1
0
499
499
1
1
1
1
1
0
0
1
1
500
500
1
1
1
1
1
0
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N2
N1
N0
Minimum
Maximum
0
0
0
1
250
500
0
0
1
1.5
166.66
333.33
0
1
0
2
125
250
0
1
1
3
83.33
166.66
1
0
0
4
62.5
125
1
0
1
6
41.66
83.33
1
1
0
8
31.25
62.5
1
1
1
12
20.83
41.66
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
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