ICS842031I-01 Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- HSTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS842031I-01
FEMTOCLOCKS™ CRYSTAL-TO- HSTL
CLOCK GENERATOR
TABLE 3E. HSTL DC CHARACTERISTICS, V_DD = V_DDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_OH
Output High Voltage; NOTE 1
V_OL
Output Low Voltage; NOTE 1
V
Output Crossover Voltage; NOTE 2
40
OX
V_SWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Typical
1.3
0.2
1.1
Maximum
60
Units
V
V
%
V
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum Typical Maximum
Fundamental
19.6
27.2
50
7
1
Units
MHz
Ω
pF
mW
TABLE
5A.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
f_OUT
tjit(Ø)
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
312.5MHz @ Integration Range:
1.875MHz - 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
NOTE 1: Please refer to the Phase Noise Plots following this section.
Minimum Typical Maximum Units
245
340
MHz
0.41
ps
350
ps
50
%
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
f_OUT
tjit(Ø)
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
312.5MHz @ Integration Range:
1.875MHz - 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
NOTE 1: Please refer to the Phase Noise Plots following this section.
Minimum Typical Maximum Units
245
340
MHz
0.52
ps
350
ps
50
%
842031AGI-01
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 21, 2005