ICS83947I Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83947I
LOW SKEW, 1-TO-9
LVCMOS FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
110
t_PD
Propagation Delay, NOTE 1
CLK to Q
1.8
4.5
tsk(o) Output Skew; NOTE 2, 5
Measured on
rising edge @V_DDO/2
500
tsk(pp) Part-to-Part Skew; NOTE 3, 5
Measured on
rising edge @V /2
2
DDO
t_PW
Output Pulse Width
tPeriod/2 - 800
tPeriod/2 + 800
t_S
Clock Enable Setup Time; NOTE 6 CLK_EN to CLK
0
t_H
Clock Enable Hold Time; NOTE 6
CLK_EN to CLK
1
t_ZL, t_ZH Output Enable Time; NOTE 4
11
t_LZ, t_HZ Output Disable Time; NOTE 4
11
t_R
Output Rise Time
0.8V to 2.0V
0.2
1
t_F
Output Fall Time
0.8V to 2.0V
0.2
1
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DD
DDO
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
Units
MHz
ns
ps
ns
ps
ns
ns
ns
ns
ns
ns
83947AYI
http://www.icst.com/products/hiperclocks.html
4
REV. B OCTOBER 11, 2004