ICS83940I-01 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4A. DC CHARACTERISTICS, V_DD = V_DDO = 3.3V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions Minimum Typical
V_IH
V_IL
V_PP
V_CMR
Input High Voltage
LVCMOS_CLK
Input Low Voltage
LVCMOS_CLK
Peak-to-Peak Input Voltage PCLK, nPCLK
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK
2.4
500
V_DD - 1.4
I_IN
Input Current
V_OH
Output High Voltage
I_OH = -20mA
2.4
V_OL
Output Low Voltage
I_OL = 20mA
I
Core Supply Current
DD
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V + 0.3V.
DD
NOTE 2: Common mode voltage is defined as V_IH.
Maximum
V_DD
0.8
1000
V_DD - 0.6
±200
0.5
25
Units
V
V
mV
V
µA
V
V
mA
TABLE
5A.
AC
CHARACTERISTICS,
V
DD
=
V
DDO
=
3.3V
±
5%,
TA
=
-40°
TO
85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
PCLK, nPCLK;
tp_LH
Propagation Delay
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
tp_LH
Propagation Delay
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
250
MHz
ns
ns
ns
ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @V_DDO/2
ps
ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f ≤ 150MHz
f ≤ 150MHz
ns
ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f > 150MHz
f > 150MHz
ns
ns
tsk(pp)
t_R, t_F
odc
Part-to-Part Skew; ^{PCLK, nPCLK}
NOTE 4, 5
LVCMOS_CLK
Output Rise/Fall Time
Output Duty Cycle
Measured on
rising edge @V_DDO/2
0.5 to 2.4V
f < 134MHz
134MHz ≤ f ≤ 250MHz
0.3
45
50
40
50
ps
ps
1.1
ns
55
%
60
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V_DDO/2.
NOTE 2: Measured from V_DD/2 to V_DDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
83940DYI-01
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 1, 2004