ICS8304 Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V_IH
Input High Voltage
2
V_IL
Input Low Voltage
-0.3
I_IH
Input High Current
V_DD = V_IN = 3.465V
I_IL
Input Low Current
V_DD = 3.465V, V_IN = 0V
-5
V_OH
Output High Voltage; NOTE 1
2.1
V_OL
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement Section,
"3.3V/2.5V Output Load Test Circuit".
V_DD + 0.3
1.3
150
0.5
Units
V
V
µA
µA
V
V
TABLE
4A.
AC
CHARACTERISTICS,
V
DD
=
V
DDO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Maximum Output Frequency
200
IJ 166MHz
2.0
3.3
tp
Propagation Delay, Low-to-High; NOTE 1
LH
166MHz < f ≤ 189.5MHz 2.0
3.4
tsk(o) Output Skew; NOTE 2, 4
ƒ= 133MHz
45
tsk(pp) Part-to-Part Skew; NOTE 3, 4
500
t_R
Output Rise Time
t
Output Fall Time
F
odc
Output Duty Cycle
30% to 70%
250
500
30% to 70%
250
500
f ≤ 189.5MHz
40
60
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ps
ps
ps
%
TABLE
4B.
AC
CHARACTERISTICS,
V
DD
=
3.3V±5%,
V
DDO
=
2.5V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Maximum Output Frequency
IJ 166MHz
2.3
tp_LH
Propagation Delay, Low-to-High; NOTE 1
166MHz < f ≤ 189.5MHz 2.15
189.5
3.7
3.55
MHz
ns
ns
tsk(o) Output Skew; NOTE 2, 4
ƒ= 133MHz
60
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
500
ps
t_R
Output Rise Time
t_F
Output Fall Time
odc
Output Duty Cycle
30% to 70%
250
30% to 70%
250
f ≤ 189.5MHz
40
500
ps
500
ps
60
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM
www.icst.com/products/hiperclocks.html
REV. F SEPTEMBER 13, 2004
4