9DBU0841 Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0841 DATASHEET
Pin Descriptions (cont.)
PIN #
PIN NAME
41 DIF6
42 DIF6#
TYPE
OUT
OUT
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
46 vOE7#
IN
47 VDDIO
PWR
48 ^CKPWRGD_PD#
IN
49 EPAD
GND
DESCRIPTION
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Connect ePAD to ground.
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100
Rs
Note: The device can drive transmission line lengths greater
than those allowed by the PCIe SIG
2pF
2pF
Driving LVDS
Driving LVDS
Cc
Rs
Cc
Rs
Device
3.3V
R7a
Zo
R8a
R7b
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
4
REVISION C 04/22/15