V103 Datasheet, PDF (3/11 Pages) Integrated Circuit Systems – TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO

V103
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
30, 31
TA+, TA-
28, 29
TB+, TB-
24, 25
TC+, TC- LVDS OUT LVDS Serial Data Output Pairs
20, 21
TD+, TD-
18, 19
TE+, TE-
22, 23
TCLK+, TCLK- LVDS OUT LVDS Reference Clock Output Pair
33, 34, 35, 36,
37, 38, 40
TA0 ~ TA6
41, 42, 44, 45,
46, 48, 49
TB0 ~ TB6
50, 52, 53, 54,
55, 57, 58
TC0 ~ TC6
IN
CMOS/TTL (or small signal) Data Bit Inputs
59, 61, 62, 63,
64, 1, 3
TD0 ~ TD6
4, 5, 6, 8, 9, 11,
16
TE0 ~ TE6
13
/PWDN
IN
High: Normal device operation
Low: Power down; all outputs become high impedance
43
RS
IN
Voltage level on this pin sets LVDS output swing voltage and data input
swing voltage; refer to the table at the bottom of this page.
60
R/F
IN
Input Clock triggering edge select. High: Rising edge; Low: Falling edge.
51, 7
VCC
Power Power supply pins for TTL inputs and digital circuitry.
12
CLKIN
IN
Clock Input.
2, 10, 39, 47,
56
GND
Ground Ground pins for TTL inputs and digital circuitry.
27
LVDSVCC
Power Power supply pins for LVDS outputs.
17, 26, 32
LVDSGND
Ground Ground pins for LVDS outputs.
15
PLLVCC
Power Power supply pin for PLL circuitry.
14
PLLGND
Ground Ground pin for PLL circuitry.
RS Input Voltage Configuration to set LVDS Output Swing and Data Input Swing
RS Input Voltage
VCC
0.6 ~ 1.4 V (VREF¹)
GND
LVDS Output Swing
350 mV
350 mV
200 mV
CMOS/TTL Input Configuration (Input Voltage Swing)
Standard Configuration¹
Small Input Swing Configuration¹
Standard Configuration¹
Note 1: Refer to DC Electrical Characteristics.
V103 Datasheet
3
11/23/06
Revision 2.0
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