ICS9DB104 Datasheet, PDF (3/13 Pages) Integrated Circuit Systems – Four Output Differential Buffer for PCI-Express

Integrated
Circuit
Systems, Inc.
ICS9DB104
General Description
ICS9DB104 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express,
next generation I/O devices. ICS9DB104 is driven by a differential input pair from a CK409/CK410 main clock generator, such
as the ICS952601 or ICS954101. ICS9DB104 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle
jitter (50ps) and output-to-output skew (50ps) requirements.
Block Diagram
2
OE1, OE6
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
HIGH_BW#
SRC_STOP#
PD#
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
STOP
4
LOGIC
DIF(1,2,5,6)
IREF
Power Groups
Pin Number
VDD
GND
1
4
5,11,18,24
4,25
28
27
28
27
Description
SRC_IN/SRC_IN#
DIF Outputs
IREF
Analog VDD & GND for PLL core
0767C—07/19/04
3