ICS952703 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for K7 System

Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Pin Description
PIN # PIN NAME
1 VDDREF
2 **FS0/REF0
3 **FS1/REF1
4 **Mode/REF2
5 GNDREF
6 X1
7 X2
8 GNDZ
9 ZCLK0
10 ZCLK1
11 VDDZ
12 SCLK
13 VDDPCI
14 *FS2/PCICLK_F0
15 *FS3/PCICLK_F1
16 PCICLK0
17 PCICLK1
18 GNDPCI
19 VDDPCI
20 PCICLK2
21 _{*(PCI_STOP#)PCICLK3}
22 _{*(CPU_STOP#)PCICLK4}
23 *(PD#)PCICLK5
24 GNDPCI
25 GND48
26 24_48MHz/SEL24_48#MHz**~
PIN
TYPE
PWR
I/O
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
PWR
IN
PWR
I/O
I/O
OUT
OUT
PWR
PWR
OUT
I/O
I/O
I/O
PWR
PWR
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Function select latch input pin, 0=Desktop Mode, 1=Mobile Mode / Ref clock output.
Ground pin for the REF outputs.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin for the ZCLK outputs
3.3V Hyperzip clock output.
3.3V Hyperzip clock output.
Power supply for ZCLK clocks, nominal 3.3V
Clock pin of I2C circuitry 5V tolerant
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
Asynchronous active low input pin used to power down the device into a low power state /
PCI clock output.
Ground pin for the PCI outputs
Ground pin for the 48MHz outputs
I/O 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
27 12_48MHz/SEL12_48#MHz*
I/O 12/48MHz clock output / Latched select input for 12/48MHz output. 0=48MHz, 1 = 12MHz.
28 AVDD48
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
29 VDDAGP
PWR Power supply for AGP clocks, nominal 3.3V
30 AGPCLK1
OUT AGP clock output
31 AGPCLK0
OUT AGP clock output
32 GNDAGP
PWR Ground pin for the AGP outputs
33 SDATA
I/O Data pin for I2C circuitry 5V tolerant
34 IREF
OUT
This pin establishes the reference current for the SRCCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
35 AGND
PWR Analog Ground pin for Core PLL
36 AVDD
PWR 3.3V Analog Power pin for Core PLL
37 CPUCLKODC0
OUT
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need
an external 1.5V pull-up.
38 CPUCLKODT0
OUT
True clock of differential pair CPU outputs. These open drain outputs need an external
1.5V pull-up.
39 GNDCPU
PWR Ground pin for the CPU outputs
40 CPUCLKODT1
OUT
True clock of differential pair CPU outputs. These open drain outputs need an external
1.5V pull-up.
41 GND
PWR Ground pin.
42 SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
43 SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
44 VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
45 GNDAPIC
PWR Ground pin for the IOAPIC outputs.
46 IOAPIC0
OUT IOAPIC clock outputs, norminal 2.5V.
47 IOAPIC1
OUT IOAPIC clock outputs, norminal 2.5V.
48 VDDLAPIC
PWR Power pin for the IOAPIC outputs. 2.5V.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
0813B—05/17/05
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