ICS94225 Datasheet, PDF (3/18 Pages) Integrated Circuit Systems – AMD-K7TM System Clock Chip

ICS94225
Byte 1: Reserved Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
Byte 2: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
Byte 3: Reserved Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 (Reserved)
Byte 4: Clock Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
7
1
1 REF0
6
23
1 24MHz/48MHz
5
22
1 USB0
4
20
1 AGP1
3
19
1 AGP0
2 42, 43 1 CPUCLKC/T2
1 39, 40 1 CPUCLKC/T1
0 36, 37 1 CPUCLKC/T0
Byte 5: PCI Clock Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
7
2
1 REF1
6
17
1 PCICLK6
5
16
1 PCICLK5
4
14
1 PCICLK4
3
13
1 PCICLK3
2
11
1 PCICLK2
1
10
1 PCICLK1
0
8
1 PCICLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0445B—08/01/03
3