ICS9248-50_1 Datasheet, PDF (3/10 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9248-50
Select Functions
Functionality
Tristate
Testmode
CPUCLK
HI - Z
TCLK/2¹
PCI,
PCI_F
HI - Z
TCLK/6¹
REF0
HI - Z
TCLK¹
SEL
TS#
100/66#
Function
0
0
Tri-State
0
-
(Reserved)
0
-
(Reserved)
0
1
Active 66.6MHz CPU, 33.3 PCI
1
0
Test Mode
1
-
(Reserved)
1
-
(Reserved)
1
1
Active 100MHz CPU, 33.3 PCI
Power Management
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN#
X
X
0
CPUCLK
Low
0
0
1
Low
0
1
1
Low
1
0
1
100/66.6MHz
1
1
1
100/66.6MHz
PCICLK
Low
Low
33.3 MHz
Low
33.3 MHz
PCICLK_F
Low
33.3MHz
33.3MHz
33.3MHz
33.3MHz
REF
Stopped
Running
Running
Running
Running
Crystal
Off
Running
Running
Running
Running
VCOs
Off
Running
Running
Running
Running
ICS9248-50 Power Management Requirements
SIGNAL
SIGNAL STATE
Latency
No. of rising edges of free
running PCICLK
CPU_ STOP#
0 (Disabled)²
1
1 (Enabled)¹
1
PCI_STOP#
0 (Disabled)²
1
1 (Enabled)¹
1
PD#
1 (Normal Operation)³
3ms
0 (Power Down)⁴
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
0278I—06/03/03
3