ICS9248-150 Datasheet, PDF (3/10 Pages) Integrated Circuit Systems – Frequency Generator for Multi - Processor Servers

ICS9248-150
Truth Table
SEL
133/100
FS0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FS1
CPUCLK PCICLK
MHz
MHZ
0
100
33
1
100
33
0
100
Disable
1
Tristate
Tristate
0
133
33
1
133
33
0
200
33
1
TCLK/2
TCLK/8
48
MHz
48
Disable
Disable
Tristate
48
Disable
48
TCLK/2
CPUCLK Buffer Configuration
Conditions
Configuration
Load
Min
Max
Iout
Vdd = nominal (3.30V)
All combinations of M0,
M1 and Rr shown in
table below
Nominal test load for
given configuration
-7% I nominal +7% I nominal
Iout
Vdd = 3.30 ± 5%
All combinations of M0,
M1 and Rr shown in
table below
Nominal test load for
given configuration
-12% I nominal +12% I nominal
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