ICS9159-05 Datasheet, PDF (3/7 Pages) Integrated Circuit Systems – Frequency Generator for Pentium™/OPTi VIPER Systems

ICS9159-05
Pin Descriptions
PIN
NUMBER
8, 20, 26
PIN NAME
VDD
1
X1
2
X2
3, 11, 23, 17 GND
6, 7, 9 CPU(0:2)
4, 5
FS(0:1)
10
15, 16, 18,
19,21, 22
12
13
ECPU
BUS(0:5)
DOZE#¹
BSEL#¹
14
STOP#¹
24
KEYBD
25
DISK
27, 28 REF (0:1)
Note:
1. Internally pulled-up
TYPE
DESCRIPTION
PWR
IN
OUT
PWR
OUT
IN
OUT
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 4-20 MHz XTAL, normally 14.318 MHz.
XTAL output which includes XTAL load capacitance.
Ground for logic, CPU and fixed frequency output buffers.
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table.
Frequency multiplier select pins. See table below. These inputs have internal pull-
up devices.
Early CPU clock. Transition precedes CPU clocks.
OUT Bus clock outputs are fixed at 1/2 the PCLK frequency.
IN
IN
OUT
OUT
OUT
Doze mode control. Reduces CPU and BUS clock frequencies by 1/2 when low.
BUS select for BSEL = 0, BUS = CPU/2
for BSEL = 1, BUS = CPU
Stop Clock. Stops all CPU clock outputs and forces them to a logic low level
synchronously with their next low level transition.
12 MHz fixed clock (with 14.318 MHz input).
24 MHz fixed clock (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
3