ICS85310I-31 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85310I-31
LOW SKEW, DUAL, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_ENA, CLK_ENB
QA0:QA4, QB0:QB4
nQA0:nQA4, nQB0:nQB4
0
Disabled; LOW
Disabled; HIGH
1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLKA, nCLKA and CLKB, nCLKB inputs as described
in Table 3B.
CLKA, nCLKB
CLKA, CLKB
CLK_ENA,
CLK_ENB
nQA0:nQA4,
nQB0:nQB4
QA0:QA4,
QB0:QB4
Disabled
Enabled
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLKA or CLKB nCLKA or nCLKB
Outputs
QA0:QA4,
QB0:QB4
nQA0:nQA4,
nQB0:nQB4
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential Non Inverting
1
0
HIGH
LOW
Differential to Differential Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential Inverting
NOTE 1: Please refer to the Application Information "Wiring The Differential Input To Accept Single Ended Levels".
85310AYI-31
www.icst.com/products/hiperclocks.html
3
REV. D JULY 6, 2005