ICS843020-01 Datasheet, PDF (3/20 Pages) Integrated Circuit Systems – FEMTOCLOCKS-TM 680MHZ, CRYSTAL-TO- 3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS843020-01
FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO-
3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
7
8, 16
9
P_DIV
V_EE
TEST
10
11, 12
V_CC
FOUT1, nFOUT1
Input
Input
Input
Input
Power
Output
Power
Output
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of
Pulldown ^{nP_LOAD input. LVCMOS / LVTTL interface levels.}
Pulldown
Pullup/
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
Input divide select. 0 = ÷8, Float = ÷1 (default), 1 = ÷4.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. LVPECL interface levels.
13
14, 15
V_CCO
Power
FOUT0, nFOUT0 Output
Output supply pin.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
17
MR
Input Pulldown inverted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not
affect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
21
V_CCA
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
22
XTAL_SEL
Input Pullup Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24, 25
26
XTAL_OUT,
XTAL_IN
nP_LOAD
Input
Input
Pulldown
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
843020AY-01
www.icst.com/products/hiperclocks.html
3
REV. B APRIL 14, 2005