ICS843002I-40 Datasheet, PDF (3/21 Pages) Integrated Circuit Systems – 175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002I-40
175MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
3
4
5
6
7
9,
10
12,
13
Name
LF1, LF0
ISET
V_CC
CLK0
nCLK0
CLK_SEL
QA_SEL1,
QA_SEL0
QB_SEL1,
QB_SEL0
Type
Analog
Input/Output
Analog
Input/Output
Description
Loop filter connection node pins.
Charge pump current setting pin.
Power
Core power supply pin.
Input
Pulldown Non-inverting differential clock input.
Input
Input
Pullup/ Inverting differential clock input.
Pulldown V_CC/2 bias voltage when left floating.
Pulldown Input clock select. LVCMOS/LVTTL interface levels. See Table 3A.
Input
Pullup LVPECL output divider control for QA/nQA outputs. See Table 3C.
Input
Pullup LVPECL output divider control for QB/nQB outputs. See Table 3C.
14
15, 16
V_CCA
QA, nQA
Power
Output
Analog supply pin.
Differential clock output pair. LVPECL interface levels.
17, 27
18, 19
V_EE
QB, nQB
Power
Output
Negative supply pins.
Differential clock output pair. LVPECL interface levels.
20
21
8, 11, 22
V_{CCO_LVPECL}
V_{CCO_LVCMOS}
nc
Power
Power
Unused
Output power supply pin for QA, nQA and QB, nQB.
Power supply pin for LOR0 and LOR1.
No connect.
23
LOR1
Output
Alarm output, loss of reference for CLK1.
LVCMOS/LVTTL interface levels.
24
LOR0
Output
Alarm output, loss of reference for CLK0.
LVCMOS/LVTTL interface levels.
25
nCLK1
Input
Pullup/ Inverting differential clock input.
Pulldown V_CC/2 bias voltage when left floating.
26
CLK1
Input
Pulldown Non-inverting differential clock input.
28,
R_SEL0,
29,
R_SEL1,
30
R_SEL2
Input
Pulldown Input divider selection. LVCMOS/LVTTL interface. See Table 3B.
31,
XTAL_OUT,
32
XTAL_IN
Input
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum Typical Maximum Units
4
pF
50
kΩ
50
kΩ
843002AKI-40
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 22, 2005