ICS8316 Datasheet, PDF (3/7 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8316
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V_DD
Inputs, V
I
Outputs, V_O
Package Thermal Impedance, θ_JA
Storage Temperature, T_STG
4.6V
-0.5V to V + 0.5 V
DD
-0.5V to V_DDO + 0.5V
34.8°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD = 3.3V, V_DDO = 1.2V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
V_DD
V_DDO
I_DD
I_DDO
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
1.14
3.3
1.2
TBD
TBD
Maximum
3.465
1.26
Units
V
V
µA
µA
TABLE 4B. LVCMOS DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V_IH
Input High Voltage
2
V_DD + 0.3
V_IL
Input Low Voltage
-0.3
0.8
CLK
I_IH
Input High Current
OEA:OED
V_DD = V_IN = 3.465V
V_DD = V_IN = 3.465V
150
5
CLK
I_IL
Input Low Current
OEA:OED
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-5
-150
V_OH
Output High Voltage
V_DDO = 1.2V ± 5%; NOTE 1
V_DD*0.7
V_OL
Output Low Voltage
V_DDO = 1.2V ± 5%; NOTE 1
V_DD*0.3
NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement section, "Load Test Circuit" diagram.
Units
V
V
µA
µA
µA
µA
V
V
TABLE 5. AC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 1.2V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
tp_LH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
3.5
TBD
150
MHz
ns
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
TBD
ps
t /t
Output Rise Time; NOTE 4
RF
odc
Output Duty Cycle
20% to 80%
650
ps
50
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V /2.
DDO
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
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