ICS548-03 Datasheet, PDF (3/4 Pages) Integrated Circuit Systems – Low Skew Clock Inverter and Divider

ADVANCE INFORMATION
ICS548-03
Low Skew Clock Inverter and Divider
Electrical Specifications
Parameter
Conditions
Minimum Typical
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
-0.5
Clock Output
Referenced to GND
-0.5
Ambient Operating Temperature
0
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3
Input High Voltage, VIH, ICLK only
ICLK (Pin 1)
(VDD/2)+1 VDD/2
Input Low Voltage, VIL, ICLK only
ICLK (Pin 1)
VDD/2
Input High Voltage, VIH
All other inputs
2
Input Low Voltage, VIL
All other inputs
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
Output High Voltage, VOH
IOH=-12mA
2.4
Output Low Voltage, VOL
IOL=12mA
IDD Operating Supply Current, 100 MHz clock S3=S2=S0=0, S1=1
TBD
Short Circuit Current
Each output
±50
Input Capacitance, S3, S2, S1, S0 , and OE
All inputs
5
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, clock input, PLL on
10
Input Frequency, clock input, PLL off
0
Output Frequency (see table on page 2)
Mode dependent
0
Output Clock Rise Time
0.8 to 2.0V
1
Output Clock Fall Time
2.0 to 0.8V
1
Output Clock Duty Cycle
at VDD/2
45
49 to 51
Output Enable Time, OE high to output on
Output Disable Time, OE low to tri-state
Absolute Clock Period Jitter, PLL modes
Deviation from mean
TBD
One Sigma Clock Period Jitter, PLL modes
TBD
Output clock skew for CLK, CLK, or CLK/2 at VDD/2
Maximum
7
VDD+0.5
VDD+0.5
70
260
150
5.5
(VDD/2)-1
0.8
0.4
120
160
120
55
50
50
500
Units
V
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
mA
mA
pF
MHz
MHz
MHz
ns
ns
%
ns
ns
ps
ps
ps
Note 1: The phase relationship between input and output clocks can change at power up. Use the ICS570 or ICS527 Zero Delay
Buffers for a guaranteed phase relationship.
External Components/Application Information
The device requires a 0.01 µF decoupling capacitor between pins 3 and 5, as close to the pins as possible.
Connect pin 2 directly to pin 3, and pin 6 directly to pin 5. Series termination resistors of 33 Ω can be used
on all used clock outputs, also close to the device. Leave any unused clock outputs floating. There are no
pull-up resistors on the input pins, so they should be connected directly to VDD or ground.
MDS 548-03
3
Revision 042700
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