ICS2495 Datasheet, PDF (3/7 Pages) Integrated Circuit Systems – Dual Video/Memory Clock Generator

Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2495 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
Depending on the load, it may be judicious to buffer XTA-
LOUT when using it to provide the system clock.
Output Circuit Considerations
As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EMI.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK or MCLK and other compo-
nents in the system should be kept as short as possible. The
ICS2495 outputs have been designed to minimize overshoot.
In addition, it may be helpful to place a ferrite bead in these
signal paths to limit the propagation of high-order harmonics
of this signal. A suitable device would be a Ferroxcube 56-590-
65/4B or equivalent. This device should be placed physically
close to the ICS2495. A 33 to 47 Ohm series resistor, some-
times called source termination, in this path may be necessary
to reduce ringing and reflection of the signal and may thereby
reduce phase jitter as well as EMI.
External Frequency Sources
EXTFREQ on versions so equipped by the programming, is
an input to a digital multiplexer. When this input is enabled by
the FS0-3 selection, the signal driving pin 2 will appear at
VCLK (15) instead of the PLL output. Internally, the PLL will
remain in lock at the frequency selected by the ROM code.
The programming option also exists to output the crystal oscil-
lator output on VCLK. In the case where XTAL1 is being
driven by an external oscillator, then this frequency would
appear on VCLK if so programmed.
Digital Inputs
FS0 (3), FS1 (4), FS2 (6), and FS3 (7), are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired. STROBE (5) when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 2. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all zeros input state. MS0 (8) and MS1 (9) are the correspond-
ing memory select inputs and are not strobed.
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ICS2495