9DBU0531 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0531 DATASHEET
Pin Descriptions
Pin# Pin Name
1 vOE4#
2 DIF4
3 DIF4#
4 VDDR1.5
5 CLK_IN
6 CLK_IN#
7 GNDR
8 GNDDIG
9 VDDDIG1.5
10 SCLK_3.3
11 SDATA_3.3
12 vOE0#
13 DIF0
14 DIF0#
15 GND
16 VDDO1.5
17 vOE1#
18 DIF1
19 DIF1#
20 GNDA
21 VDDA1.5
22 DIF2
23 DIF2#
24 vOE2#
25 VDDO1.5
26 GND
27 DIF3
28 DIF3#
29 vOE3#
30 GND
31 ^CKPWRGD_PD#
32 ^SADR_tri
33 EPAD
Type Pin Description
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR ^{1.5V power for differential input clock (receiver). This VDD should be treated}
as an Analog power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Analog Ground pin for the differential input (receiver)
GND Ground pin for digital circuitry
PWR 1.5V digital power (dirty power)
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin.
PWR Power supply for outputs, nominally 1.5V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.5V power for the PLL core.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for outputs, nominally 1.5V.
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high
IN assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection
IN Table.
GND Connect ePAD to ground.
REVISION D 04/22/15
3
5 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER