ICS952621 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

Integrated
Circuit
Systems, Inc.
Pin Description
PIN
PIN NAME
#
1 FS_A/REF1
2 FS_B/REF0
3 VDDREF
4 X1
5 X2
6 GND
7 PCICLK_F0
8 PCICLK_F1
9 PCICLK_F2
10 VDDPCI
11 GND
12 PCICLK0
13 PCICLK1
14 PCICLK2
15 PCICLK3
16 VDDPCI
17 GND
18 PCICLK4
19 PCICLK5
20 PD#
21 48MHz_DOT
22 48MHz_USB
23 GND
24 VDD48
25 3V66_3/VCH
26 3V66_2
27 VDD3V66
28 GND
29 3V66_1
30 3V66_0
31 SCLK
32 SDATA
33 VttPWR_GD#
34 VDD
35 SRCCLKC
36 SRCCLKT
37 GND
38 CPUCLKC0
39 CPUCLKT0
40 VDDCPU
41 CPUCLKC1
42 CPUCLKT1
43 GND
44 CPUCLKC_ITP
45 CPUCLKT_ITP
46 IREF
47 GND
48 VDDA
0756A—09/10/04
PIN TYPE
DESCRIPTION
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
OUT
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
OUT
PWR
PWR
FS_A latched input for frequency select
Reference output, 14.318Hz
FS_B latched input for frequency select
Reference output, 14.318Hz
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used
to power down the device. The internal clocks are disabled and the VCO and
the crystal are stopped.
48.008MHz Dot clock output
48.008MHz USB clock output
Ground pin.
Power for 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output
VCH: 48MHz VCH clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch
inputs are valid and are ready to be sampled. This is an active low input.
Power supply, nominal 3.3V
Complementary clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
"Complementary" clocks of differential pair CPU outputs for ITP.. These are
current mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs for ITP. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin.
3.3V power for the PLL core.
2
ICS952621