ICS94241 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Programmable TCH™ for Differential PIII™ Processor

ICS94241
General Description
The ICS94241 is a single chip timing control hub for desktop designs using VIA PL133-T style chipset with Intel
differential PIII processor. It provides all necessary clock signals for such a system.
The ICS94241 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub).
ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock
device. This part incorporates ICS's newest clock technology which more robust features and functionality.
Employing the use of a serially programmable I²C interface, this device can adjust the output clocks by
configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output
skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's
Watchdog Timer technology in having a frequency reset feature to provide a safe setting under unstable system
conditions.
Pin Configuration
PIN NUMBER
1, 5, 14, 19, 30, 36
PIN NAME
VDD
TYPE
DESCRIPTION
PWR Power supply, nominal 3.3V
2, 8, 16, 22, 33, 39, 45 GND
3
X1
4
X2
FS4^1,3
6
PCICLK0
FS3^1,3
7
PCICLK1
13, 12, 11, 10, 9 PCICLK (6:2)
15
17, 18, 20, 21, 28, 29,
31, 32, 34, 34, 35, 37,
38, 40
23
BUFFER IN
SDRAM (12:0)
SDATA
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
IN
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load cap
(36pF)
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset)
I/O Data pin for I²C circuitry 5V tolerant
24
SCLK
IN Clock pin of I²C circuitry 5V tolerant
FS1^2,3
25
24MHz
IN Frequency select pin. Latched Input.
OUT 24MHz output clock
48MHz
26
FS0^2,3
OUT 48MHz output clock
IN Frequency select pin. Latched Input
27
AVDD48
PWR Analog power for 48MHz outputs
41
RESET
OUT
Real time system reset signal for frequency ratio change or
watchdog timmer timeout. This signal is active low.
42
VDDLCPU
PWR Supply for CPU clocks 2.5V nominal
43
CPUCLK0
OUT CPU clock outputs
44
CPUCLK_CS
OUT CPU clock output for chipset host clock
FS2^2,3
46
REF1
IN Frequency select pin. Latched Input
OUT 14.318 MHz reference clock.
47
REF0
OUT 14.318 Mhz reference clock.
This 3.3V LVTTL input is a level sensitive strobe used to determine
48
VTT_PWRGD#
IN when FS inputs are valid and are ready to be sampled
(active low)
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Internal Pull-down to GND on indicated inputs
3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0453C—10/26/04
2