ICS94209 Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – Programmable Frequency Generator & Integrated Buffers for Pentium III Processor

ICS94209
General Description
The ICS94209 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary clock
signals for such a system.
The ICS94209 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I²C interface as a vehicle for changing output
functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread
spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety
'Watchdog Timer' technology which will reset the frequency
to a safe setting if the system becomes unstable from over
clocking.
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
MODE Pin Power Management Control Input
MODE
Pin 21
Pin 27
Pin 28
Pin 30
Pin 31
0
SDRAM11 SDRAM10
SDRAM9
SDRAM8
1 CPU_STOP# PCI_STOP# SDRAM_STOP# PD#
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43
2
3
4, 14, 18, 19, 29,
32, 39, 44
5
6
8
9
13, 12, 11, 10
17, 16,
20
PIN NAME
VDD
A G P S EL
REF0
FS3
REF1
GND
X1
X2
FS1
P CIC LK _F
FS2
P CIC LK 0
PCICLK (4:1)
A G P (1:0)
FS0
48M H z
MODE
21
24_48MHz
23
S D A TA
24
SCLK
CPU_STOP#
27
SDRAM11
28
PCI_STOP#
SDRAM10
SDRAM9
30
S D RA M _STO P #
PD#
31
SDRAM8
26 33, 34, 36, 37,
SD RA M (12, 7:0)
38, 40, 41, 42
45, 46, 47
CPUCLK (2:0)
48
VDDL
TYPE
PWR
IN
OUT
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
I/O
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
PWR
D ES C R IPTION
3.3V P ow er supply for SD RA M output buffers, PCI output buffers,
reference output buffers and 48M H z output
A G P frequency select pin.
14.318 M H z reference clock.
Frequency select pin.
14.318 M H z reference clock.
G round pin for 3V outputs.
Crystal input,nominally 14.318M H z.
Crystal output, nominally 14.318M H z.
Frequency select pin.
P CI clock output, not affected by P CI_STO P #
Frequency select pin.
P CI clock output.
P CI clock outputs.
A G P outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48M H z output clock
P in 27, 28, 30, & 31 function select pin
0=D esktop 1=M obile mode
Clock output for super I/O /U S B default is 24M H z
D ata pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
S tops all PCICLK s besides the PCICLK _F clocks at logic 0 level, w hen input
is low and M O D E pin is in M obile mode
S D RA M clock output
S tops all CPU CLK s clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
S D RA M clock output
S D RA M clock output
S tops all SD RA M clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
A synchronous active low input pin used to pow er dow n the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the pow er dow n w ill not be greater than 3ms.
S D RA M clock output
S D RA M clock outputs
CPU clock outputs.
P ow er pin for the CP U CLK s. 2.5V
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