ICS9341 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – 133MHz Clock Generator and Integrated Buffer for PowerPC™

ICS9341
Pin Descriptions
Pin number
Pin name
1
G N D REF
2
X1
3
X2
4, 16
VDDPCI
5, 6, 7, 8, 17, 18, _{PCICLK (1:8)}
19, 20
9, 24
GNDPCI
10
GNDCPUB
11, 12, 13, 14 CPUB (1:4)
15
VDDCPUB
21, 22
FS (0:1)
23, 41
*O UT_SEL (0:1)
24
25
26
27, 28
29
30
31
GNDPCI
VDDA
*PCI_STOP#
N /C
GNDD
GNDA
GNDOUT
32
O U T/2
33
OUT
34
VDDOUT
35
VDDD
36
CPUB_STOP#**
45, 44, 38, 37 CPUA (1:4)
39
VDDCPUA
40
PD#
42
43
46
47, 48
GNDCPUA
SS_EN
V D D REF
REF
Type
PWR
IN
OUT
PWR
OUT
PWR
PWR
OUT
PWR
IN
IN
PWR
PWR
IN
-
PWR
PWR
PWR
OUT
OUT
PWR
PWR
IN
OUT
PWR
IN
PWR
IN
PWR
OUT
D escription
Ground pin for REF clocks.
XTAL_IN 14.318M Hz crystal input.
XTAL_OUT Crystal output.
3.3Volts power pin for PCICLKs.
PCI clock output at 3.3V . Synchronous to CPU clocks.
Ground pin for PCI clocks.
Ground pin for CPUB clocks.
CPUCLK outputs up to 133.3M Hz.
Pow er pin for the CPU bank B CLK s. 3.3V.
Logic - input for frequency selection.
These control the output functionality of the O UT and O UT/2 pins.
Refer to table for details.
Gnd pin for PCICLK s.
Pow er for analog outputs.
This active low input stops PCI clocks.
Not connected
Digitial ground
Analog ground
Ground for output pins.
Half the O UT frequency. Dependent on OUT_SEL. Refer to table
for details.
This output frequency is dependent on OU T_SEL. Refer to table for
d etails .
Pow er for OUT pins 3.3V .
Pow er for digitial outputs.
This active low input stops the CPUB clocks at a logic "0" level
when input low .
CPUCLK outputs up to 133.3M Hz.
Pow er pin for the CPU bank A CLKs. 3.3V .
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
Ground pin for CPUB clocks.
Spread spectrum is turned on by driving this input high and turned
off by driving low.
Pow er pin for REF clocks.
14.318M Hz reference clock outputs at 3.3V.
2