ICS9248-185 Datasheet, PDF (2/11 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6

ICS9248 - 185
General Description
The ICS9248-185 is the single chip clock solution for Notebook designs using the 440BX or the VIA Apollo Pro 133 style
chipset. It provides all necessary clock signals for such a system. The ICS9248-185 provides CPU and PCI clocks with
continous spread spectrum. The ICS9248-185 employs a proprietary closed loop design, which tightly controls the percentage
of spreading over process and temperature variations.
Pin Descriptions
PIN
NUMBER
PIN NAME
1, 6, 15, 18, VDD
2
REF0
3, 8, 13,
19, 24
4
5
7
9
10
11
GND
X1
X2
PCICLK_F
FS1^{1, 2}
PCICLK0
BUFFER IN
PCICLK1
12
PCI_STOP#
14
16, 17, 20,
21
22
FS0^{1, 2}
48MHz
SDRAM (4:1)
SDRAM0/_F
23
CLK_STOP#
25
CPUCLK1
26
CPUCLK0/_F
27
VDDL
28
FREE_SEL
REF1
TYPE
DESCRIPTION
PWR Power supply, nominal 3.3V
OUT
14.318 Mhz reference clock.This REF output is the STRONGER buffer
for ISA BUS loads
PWR Ground
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
PWR
IN
OUT
Crystal input, has internal load cap (36pF) and feedback resistor from X2
Crystal output, nominally 14.318MHz.
Free running PCI clock not affected by PCI_STOP# for power management.
Frequency select pin. Latched Input.
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Input to Fanout Buffers for SDRAM outputs.
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Halts PCICLK clocks at logic 0 level, when input low
(In mobile mode, MODE=0)
Frequency select pin. Latched Input
48MHz output clock
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Either free running SDRAM or stoppable depending on FREE_SEL
This asynchronous input halts CPUCLKs, & SDRAMs at logic "0" level
when driven low.
CPU clock output, powered by VDDL
Either free running CPUCLK or stoppable depending on FREE_SEL
Supply for CPU clocks 2.5V
Selects CPUCLK0/_F and SDRAM0/_F to be either free running or
stoppable by CLK_STOP#. When FREE_SEL is set to (0) low the above
clocks are free running - when set to (1) high, the clocks are stoppable.
14.318 MHz reference clock.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2