ICS9248-163 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – AMD - K7 System Clock Chip

ICS9248-163
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,
33,39,45, 47
4
PIN NAME
VDDREF
REF0
CPU_STOP#^{1, 2}
GND
X1
5
6
7
8
10
13, 12, 11
14
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
19,30,36
23
24
25
26
27
40
41
42
43
X2
VDD
PCICLK_F
MODE^{1, 2}
FS3^{1, 2}
PCICLK0
SEL24_48#^{1, 2}
PCICLK1
PCICLK (4:2)
VDDPCI
BUFFER IN
SDRAM (11:0)
VDDSDR
SDATA
SCLK
24_48MHz
FS1^{1, 2}
48MHz
FS0^{1, 2}
VDD48
SDRAM_OUT
PD#
VDDA
CPUCLKT0
44
CPUCLKC0
46
CPUCLK
REF1
48
FS2^{1, 2}
TYPE
PWR
OUT
IN
DESCRIPTION
REF, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM
(11:0) at logic "0" level when driven low.
PWR Ground
IN
OUT
PWR
OUT
IN
IN
OUT
IN
OUT
OUT
PWR
IN
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Supply for internal digital logic
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-up to VDD
PCI clock output
Logic input to select 24 or 48MHz for pin 25 output
PCI clock output.
PCI clock outputs.
Supply for PCICLK_F and PCICLK, nominal 3.3V
Input to Fanout Buffers for SDRAM outputs.
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
PWR
I/O
IN
OUT
IN
OUT
IN
PWR
OUT
IN
PWR
OUT
OUT
OUT
OUT
IN
Supply for SDRAM 9nominal 3.3V.
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
24MHz/48MHz clock output
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
Reference clock for SDRAM buffer
Powers down chip, active low
Supply for core, & CPU 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
3.3V CPU clock output powered by VDDA
14.318 MHz reference clock.
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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