ICS9248-157 Datasheet, PDF (2/11 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9248-157
Advance Information
General Description
The ICS9248-157 is the Main clock solution for Notebook designs using the Intel ALI1621/1632M style chipset. Along with
an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding.
The ICS9248-157 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process
and temperature variations.
Pin Descriptions
Pin number
1
2
3
4
5
11, 10, 9, 6
7, 15, 21
8
12
13
14
16
Pin name
FS1
RE F0
X1
X2
FS2
P CI CLK _F
S E L_CP UF#
P CI CLK 0
PCICLK (4:1)
GND
VDDPCI
P CI CLK _E
V DD48
FS3
48MHz
DIV4#
17
PD#
18
CP U_S T O P #
19
V DDA
20
P CI-S T O P #
22
GNDL
23
CPUCLK0/F
24
CP UCLK 1
25
VDDL
26
SPREAD#
27
FS0
RE F1
28
V DDR
Type
Input
Output
Input
Output
Input
Output
Input
Output
Output
P ower
P ower
Output
P ower
Input
Output
Input
Input
Input
Power
Input
P ower
Output
0utput
P ower
Input
Input
Output
Power
D es c rip tio n
Frequency select pin
3.3V, 14.318 MHz reference clock output.
14.318 MHz crystal input
14.318 MHz crystal output
Frequency select pin
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
Active low input to select CPUCLK0/F (pin 23) either normal CPUCLK or Free
running (not stoppable through CPU_STOP#) clock.
3.3V PCI clock output
3.3 V PCI clock outputs, generating timing requirements
Ground for clock outputs
3.3 V power for the PCI clock outputs
Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#
3.3 V power for 48 MHz clocks
Frequency select pin
Fixed 48MHz clock.
Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular
f requec ies
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
3.3 V power for the core
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
Ground for the CPU and Host clock outputs
2.5V CPU clock output; can be selected to be free running by driving
SEL_CPUF# low
2.5 V CPU and Host clock outputs
2.5 V power for the CPU and Host clock outputs
power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
Frequency select pin
3.3V, 14.318 MHz reference clock output.
3.3 V power for the REFCLK and crystal clock outputs
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