ICS9248-143 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM II/IIITM & K6

ICS9248 - 143
Pin Descriptions
PIN
NUMBER
1
2
20
3, 9, 16,
33, 40, 44
4
5
6,14
7
8
10
11
17, 13, 12
15
18
19
PIN NAME
VDDREF
SPREAD^1,2
REF0
PCI_STOP#
GND
X1
X2
VDDPCI
CPU2.5_3.3#^1,2
PCICLK_F
FS3^1,2
PCICLK0
SEL24_48#^1,2
PCICLK1
SELPCIE_6#^1,2
PCICLK2
PCICLK (5:3)
BUFFER IN
PCICLK6/PCICLK_E
VDDCOR
21
PD#¹
22
28, 29, 31, 32,
34, 35, 37, 38
30, 36
23
24
25
26
27
39
41
42, 43, 45
46
47
48
GND48
SDRAM (7:0)
VDDSDR
SDATA
SCLK
24_48MHz
FS1^{1, 2}
48MHz
FS0^{1, 2}
VDD48
SDRAM_F
CLK_STOP#
CPUCLK (2:0)
CPUCLK_F
VDDLCPU
REF1
FS2^{1, 2}
TYPE
PWR
IN
OUT
IN
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Active High Spread Spectrum enable input. Power-up default is "High", spreading is "on"
14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads
Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0)
PWR
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
PWR
IN
PWR
OUT
PWR
IN
IN
OUT
IN
OUT
IN
PWR
OUT
IN
OUT
OUT
PWR
OUT
IN
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz.
Supply for PCICLK_F and PCICLK nominal 3.3V
Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input.
Free running PCI clock not affected by PCI_STOP# for power management.
Frequency select pin. Latched Input.
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Selects either 24 or 48MHz when Low =48 MHz
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
PCI Early or normal PCI select latch input. (for pin 18 power-up default is "High" early PCICLK.)
PCICLK clock output.
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Input to Fanout Buffers for SDRAM outputs.
PCI clock output or early PCI clock output selectable by SELPCIE_6#
Power pin for the PLL core. 3.3V
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power
down will not be greater than 4ms.
Ground pin for the 24 & 48MHz output buffers & fixed PLL core.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset).
Supply for SDRAM and CPU PLL Core, nominal 3.3V.
Data input for I²C serial input, 5V tolerant input
Clock input of I²C input, 5V tolerant input
24MHz or 48MHz output clock selectable by pin 10
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK, & SDRAM at logic "0" level when driven low.
CPU clock outputs, powered by VDDLCPU
Free running CPU clock. Not affected by the CPU_STOP#
Supply for CPU clocks 2.5V
14.318 MHz reference clock.
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2