ICS9248-136 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for K7 Processor

ICS9248-136
Advance Information
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43, 48
2
3
4, 14, 18, 19, 29,
32, 39, 44
5
6
8
9
13, 12, 11, 10
17, 16
20
PIN NAME
VDD
AGPSEL
REF1
FS3
REF0
GND
X1
X2
FS1
PCICLK_F
FS2
PCICLK0
PCICLK (4:1)
AGPCLK (1:0)
FS0
48MHz
MODE
21
24_48M H z
23
SDATA
24
SCLK
CP U _S TO P #
27
SDRAM11
28
P CI_S TO P #
SDRAM10
S D RA M _S TO P #
30
SDRAM9
PD#
31
SDRAM8
26, 33, 34, 36, 37,
SDRAM (12, 7:0)
38, 40, 41, 42
46
CPUCLKC0
45, 47
CPUCLKT (1:0)
TY PE
PWR
IN
OUT
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
I/O
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48M Hz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=M obile mode
Clock output for super I/O/USB default is 24M Hz
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
Stops all CPUCLKs clocks at logic 0 level, when input low
(when M ODE active).
SDRAM clock output
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low (when M ODE active).
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input low
(when M ODE active)
SDRAM clock output
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms. (when
M ODE active)
SDRAM clock output
SDRAM clock outputs
Complementory"" clocks of differential pair CPU outputs. These clocks are
180° out of phase with SDRAM clocks. These open drain outputs need an
external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase with
SDRAM clocks. These open drain outputs need an external 1.5V pull-up.
Third party brands and names are the property of their respective owners.
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