ICS9248-135 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™& K6

ICS9248-135
General Description
The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-135
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I²C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER PIN NAME
1, 6, 15, 19, 27,
30, 36, 42
2
3, 10, 16, 22, 33,
39, 44
4
5
7
VDD
REF0
FS3
GND
X1
X2
FS1
PCICLK_F
8
14, 13, 12, 11, 9
FS2
PCICLK1
PCICLK (6:2)
17
SDRAM_STOP#
18
PD#
20
21
38, 37, 35, 34,
32, 31, 29, 28
23
24
25
26
41, 40
45, 43
46
47
48
CPU_STOP#
PCI_STOP#
SDRAM (7:0)
SDATA
SCLK
CPU2.5_3.3#
24_48MHz
FS0
48MHz
SDRAM_F (1:0)
CPUCLK (1:2)
CPUCLK_F
VDDLCPU
REF1
TYPE
PWR
OUT
IN
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
PWR
OUT
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
14.318 MHz reference clock.
Frequency select pin.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
Free running PCICLK clock output. Not affected by PCI_STOP#
Frequency select pin.
PCI clock outputs.
PCI clock outputs.
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Stops all CPUCLKs clocks at logic 0 level, when input low
Stops all PCICLKs clocks at logic 0 level, when input low
SDRAM clock outputs
Data input for I²C serial input, 5V tolerant input
Clock input of I²C input, 5V tolerant input
Voltage select 2.5V when high - 3.3V when low
Clock output for super I/O/USB default is 24MHz
Frequency select pin.
48MHz output clock
Free running SDRAM clock outputs. Not affected by SDRAM_STOP#
CPU clock outputs.
Free running CPUCLK clock output. Not affected by CPU_STOP#
Power pin for the CPUCLKs. 2.5V
14.318 MHz reference clock.
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