ICS9248-103 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9248 - 103
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
2
20
3, 9, 16,
33, 40, 44
4
5
VDDREF
REF0
PCI_STOP#
GND
X1
X2
PWR
OUT
IN
Ref, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
Halts PCICLK [4:0]clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
PWR Ground
IN
OUT
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz.
6,14
7
8
10
11
18, 17, 13,
12
15
VDDPCI
CPU2.5_3.3#^1,2
PCICLK_F0
FS3^1,2
PCICLK_F1
SEL24_48#MHz^1,2
PCICLK_F2
PCICLK1
PCICLK [5:2]
BUFFER IN
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
Supply for PCICLK_F and PCICLK [6:0], nominal 3.3V
Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU,
LOW=3.3V CPU. Latched Input.
Free running PCI clock not affected by PCI_STOP# for power
management.
Frequency select pin. Latched Input.
Free running PCI clock not affected by PCI_STOP# for power
management.
Selects either 24 or 48MHz when Low = 48MHz
Free running PCI clock not affected by PCI_STOP# for power
management.
PCI clock output Synchronous to CPU clocks with 1-4ns skew (CPU
early)
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
19
VDDCOR
21
PD#¹
22
GND48
PWR
IN
PWR
Power pin for the PLL core. 3.3V
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are disabled
and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 4ms.
Ground pin for 24 & 48MHz output buffers & fixed PLL core.
28, 29, 31, 32,
34, 35, 37, 38
SDRAM [7:0]
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
30, 36
23
VDDSDR
SDATA
PWR Supply for SDRAM [7:0] and CPU PLL Core, nominal 3.3V.
IN Data input for I²C serial input, 5V tolerant input
24
SCLK
IN Clock input of I²C input, 5V tolerant input
24_48MHz
25
FS1^{1, 2}
OUT 24MHz or 48MHz output clock selectable by pin 10
IN Frequency select pin. Latched Input.
48MHz
26
FS0^{1, 2}
OUT 48MHz output clock
IN Frequency select pin. Latched Input
27
VDD48
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
39
SDRAM_F
OUT Free running SDRAM clock output. Not affected by CPU_STOP#
41
CLK_STOP#
IN
This asynchronous input halts CPUCLK & SDRAM (0:7) at logic
"0" level when driven low.
42, 43, 45
CPUCLK [2:0]
OUT CPU clock outputs, powered by VDDLCPU
46
CPUCLK_F
OUT Free running CPU clock. Not affected by the CPU_STOP#
47
VDDLCPU
PWR Supply for CPU clocks 2.5V
REF1
48
FS2^{1, 2}
OUT 14.318 MHz reference clock.
IN Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2