ICS9169C-272 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Frequency Generator for Pentium™ Based Systems

ICS9169C-272
Pin Descriptions
PIN NUMBER
1
PIN NAME
VDD
2
X1
TYPE
PWR
IN
3
4,11,20,26
5
6,7,9,10,15,16,17,18,19
8
12
13
14
21,22,24,25,27,28
23
29
30
31
32
X2
GND
CPU(1)
FS0
CPU
(2:5) (8:12)
VDDC1
CPU(6)
FS1
CPU(7)
FS2
VDDC2
BUS (1:6)
VDDB
VDDF
24MHz
48MHz
REF
BSEL
OUT
PWR
OUT
IN
OUT
PWR
OUT
IN
OUT
IN
PWR
OUT
PWR
PWR
OUT
OUT
OUT
IN
* The internal pull up will vary from 350K to 500K based on temperature
DESCRIPTION
Power for device logic and crystal oscillator circuit and
14.318 MHz output.
XTAL or external reference frequency input. This input
includes XTAL load capacitance and feedback bias for a
12-16M Hz crystal, nominally 14.31818M Hz external crystal
load of 30pF to GND recommended for VDD power on faster
than 2.0ms.
XTAL output which includes XTAL load capacitance.
External crystal load of 10pF to GND recommended for VDD
power on faster than 2.0ms.
Ground for device logic.
Processor clock output which is a multiple of the input
reference frequency.
Frequency multiplier select pins. 350K internal pull up.
Processor clock outputs which are a multiple of the input
reference frequency.
Power for CPU(1:6) output buffers only. Can be reduced VDD
for 2.5V (2.375-2.62V) next generation processor clocks.
Processor clock output which is a multiple of the input
reference frequency internal pull up devices.
Frequency multiplier select pin. See shared pin description.
350K internal pull up.
Processor clock output which is a multiple of the input
reference frequency internal pull up devices.
Frequency multiplier select pin. See shared pin description.
350K internal pull up.
Power for CPU PLL, logic and CPU(7:12)output buffers. M ust
be nominal 3.3V (3.0 to 3.7V).
BUS clock outputs which are a multiple of the input reference
clock.
Power for BUS clock buffers BUS(1:6).
Power for fixed clock buffer (48 MHz, 24 Mhz).
Fixed 24MHz clock (assuming a 14.31818MHz REF
frequency).
Fixed 48MHz clock (assuming a 14.31818MHz REF
frequency).
Fixed 14.31818M Hz clock (assuming a 14.31818M Hz REF
frequency).
Selection for synchronous or asynchronous bus clock
operation. See shared pin programming description late in this
data sheet for further explanation. 350K internal pull up.
2