ICS9159-20 Datasheet, PDF (2/5 Pages) Integrated Circuit Systems – Frequency Generator for SIS551X and SIS6205 Chip Set Systems

ICS9159-20
Pin Descriptions
PIN NUMBER
1, 8, 20, 26
2
PIN NAME
VDD
X1
3
4, 11, 17, 23
5
6, 7, 9, 10, 24
13, 12
X2
GND
BSEL
BOUT(0:4)
FS(0:1)
15, 16, 18, 19,
21, 22, 27
BCLK(0:6)
28
REF
TYPE
PWR
IN
OUT
PWR
IN
OUT
IN
OUT
OUT
DESCRIPTION
Power for logic, PCLK and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz.
XTAL output which includes XTAL load capacitance.
Ground for logic, PCLK and fixed frequency output buffers.
The DISK controller clock is fixed at 33 MHz (with 14.318 MHz input).
Uncommitted clock buffer outputs.
Frequency multiplier select pins. See table above. These inputs have internal pull-up
devices. 14 BIN IN Uncommitted buffered inputs.
Bus clock outputs are fixed at 33.3 MHz or one half the CPU frequency. 25 CPU
OUT Processor clock outputs which are a multiple of the input reference frequency
as shown in the table above.
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
Note: BCLK buffers cannot be supplied with 5 volts (Pins 14 and 20) if CPU and fixed frequencies (Pins 1, 8 and 26) are being
supplied with 3.3 volts.
2