ICS9159-06 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Frequency Generator and Buffer for Pentium Systems

ICS9159-06
Preliminary Product Preview
Pin Configuration
28-Pin 300-mil SOIC
Pin Descriptions
PIN NUMBER PIN NAME
8, 26
VDD
1
X1
2
3, 11, 23
X2
GND
6, 7, 9
CPU(0:2)
4, 5
FS(0:1)
20
15, 16, 18 19,
21, 22
24, 25, 27, 28
VDDB
BUS(0:5)
REF(0:3)
10
ECPU
12
DOZE#
13, 14
STP0#, STP1#
17
GNDB
TYPE
PWR
IN
OUT
PWR
OUT
IN
PWR
OUT
OUT
OUT
IN
IN
PWR
DESCRIPTION
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 0.5 - 20 MHz XTAL.**
XTAL output which includes XTAL load capacitance.**
Ground for logic, CPU and fixed frequency output buffers.
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table.
Frequency multiplier select pins. See table. These inputs have internal pull-up
devices.
Power for BUS output buffers.
Bus clock outputs are fixed at 33.3 or 16.7 MHz.*
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.*
Early processor clock output which is the same frequency as CPU(0:2). This clock
leads CPU(0:2) by 3-6nS.
Reduces CPU, ECPU and BUS clock outputs as shown in the functionality table
when at a logic low level.
Synchronously stops the CPU, ECPU and BUS clocks per the description in the
functionality table. Can also be used to tristate all outputs when the DOZE pin is
low.
This ground return path is brought on separately to permit separating the noise
impulses from high output buffers from affecting sensitive internal circuitry.***
* Assuming 14.31818 MHz input clock or crystal.
* * Device provides 18pF load for crystal load capacitance at each pin.
*** Ground for bus clock buffers.
2