ICS9150-01 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – Pentium Pro™ and SDRAM Frequency Generator

ICS9150- 01
Pin Descriptions
PIN NUM BER
3
4, 10, 17, 23, 31,
34, 40, 47, 53
5
6
PIN NAM E
REF0
GND
X1
X2
29
MODE
8
9, 11, 12, 13
14, 16
PCICLK_F
PCICLK (0:5)
30
FS0
27
28
1, 7, 15, 20, 26,
37, 43
SDATA
SCLK
VDD2, VDD1,
VDD, VDD3
50, 56
VDDL2, VDDL1
18, 19, 21, 22, 24,
25, 32, 33, 35, 36, SDRAM (0:11)
38, 39, 41, 42, 44, (14:15)
45
2, 54, 55
IOAPIC (0:2)
46, 48, 49, 51, 52 CPUCLK (0:4)
32
SDRAM13
CPU_STOP#
33
SDRAM12
PCI_STOP#
TYPE
D ES CR IPTION
OUT 14.318 MHz reference clock outputs.
PWR Ground.
IN
OUT
IN
OUT
14.318MHz input. Has internal load cap.
Crystal output. Has internal load cap and feedback resistor to X1
Mode select pin for enabling power management features,
has pullup.
Free running BUS clock during PCI_STOP#=0.
OUT BUS clock outputs.
IN
Select pin for enabling 66.6 MHz or 60 MHz. CPU/SDRAM clock
frequency
IN Serial data in for serial config port.
IN Clock input for serial config port.
PWR Nominal 3.3V power supply, see power groups for function.
PWR
CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V
nominal.
OUT SDRAM clocks (60/66.6MHz)
OUT
OUT
OUT
IN
OUT
IN
IOAPIC clock output. (14.31818 MHz) Poweredby VDDL1
CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
SDRAM clock (60/66.6 MHz)
Halts CPUCLK clocks at logic "0" level when low.
SDRAM clock (60/66.6 MHz)
Halts PCICLK (0:5) at logic "0" level when low.
Power Groups
VDD = Supply for PLL core
VDD1 = REF 0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:11) (14:15), SDRAM13/CPU_STOP#, SDRAM12/PCI_STOP#
VDDL1 = IOAPIC (0:2)
VDDL2 = CPUCLK (0:4)
2